\section{Motivation}
\label{sec:introduction}
Over the past several decades,
Dennard-style scaling of Metal
Oxide Semiconductor Field Effect Transistors (MOSFETs) has driven the
constant enhancements in speed, energy efficiency and functionality of
digital systems. However, recent trends show an unwanted, but
anticipated, slowdown in the power/performance improvement from
transistor scaling. This is due to several detrimental effects that
have surfaced in deeply scaled technologies, such as aggravation of
short channel effects and larger sensitivity of devices to process
variations~\cite{Borkar-DAC2003-Variations}.
Therefore, alternate device structures
including materials other than silicon are being explored to sustain
the benefits of technology scaling. Moreover, instead of following the
conventional approach of designing transistors for general
applications, circuit/system-aware device design is being actively
pursued. Specifically, an upsurge in the demand for low power mobile
systems has led to the exploration of energy efficient devices.


% like direct source-drain tunneling~\cite{Vega-TED2009-DSDT}.

% ~\cite{Hisamoto-TED2000-FinFETs}
 
% (also known as near-threshold operation)
% ~\cite{Dreslinski-PIEEE2010-NTC}. Hence, devices which are suitable
% for near threshold operation are being actively explored.

The most effective method to maximize energy efficiency is to operate
circuits at a $V_{DD}$ close to the transistor threshold voltage.  Amongst
such low power devices, the band-to-band tunnel
FET(TFET)~\cite{Mookerjea-DRC2008-TFETs} is one the most promising
transistor architectures due to its steeper switching characteristics
compared to standard transistors. Steeper switching characteristics
permit more aggressive $V_{DD}$ scaling in TFET-based circuits, which
leads to significantly higher energy efficiency in the near-threshold
region.

However, TFETs have their own design issues and limitations, due to
which it is not straight-forward to use TFETs as a drop-in replacement
for standard transistors in low power
circuits~\cite{Singh-ASPDAC2010-TFETSRAM}. The steep sub-threshold
slope of TFETs increases their sensitivity to process variations. TFETs
exhibit asymmetric output characteristics, which are not desirable for
circuits like flip-flops requiring bi-directional current. The Miller
capacitance is larger in TFETs
~\cite{Mookerjea-EDL2009-TFETMillerCap}, which may increase the
dynamic energy consumption. Hence, in order to overcome the
limitations of TFETs and harness their full potential, novel circuit
and architecture techniques are required.  Existing works on circuit
and architecture designs based on TFETs address some of the issues
described
above~\cite{Swaminathan_SystemLevelTFET_ISCA14};
however there is limited work on exploration of cross-layer design
techniques with a proper consideration of process variations in the
analyses.

\textbf{In this research, we propose technology-aware circuit-architecture
co-design techniques for TFET-based processors to achieve higher
energy efficiency and robustness to process variations.} Using
physics-based device models, the circuit and architectural
implications of TFETs will be analyzed considering process variations.
Novel circuit and architecture techniques will be explored and
cross-layer optimization methodologies will be developed to enhance
the effectiveness of TFETs for low power near-threshold operation.

% LocalWords:  Dennardian multicore uniprocessor superlinear SPECINT Dennard
% LocalWords:  CMP ARM's tradeoffs ALU tuple MOSFETs etcetera FinFETs VDD FET


% LocalWords:  TFET TFETs analyses
